

`include "defines.v"

module wb_stage(
  input wire rst,
  input wire [4:0]inst_type_i,
  input wire rd_w_ena_i,
  input wire [4:0]rd_w_addr_i,
  input wire [`REG_BUS]rd_w_data_i,
  input wire [31:0]inst_i,
  input wire [`REG_BUS]pc_i,

  output wire [4:0]inst_type_o,
  output wire rd_w_ena_o,
  output wire [4:0]rd_w_addr_o,
  output wire [`REG_BUS]rd_w_data_o,
  output wire [31:0]inst_o,
  output wire [`REG_BUS]pc_o
);

  
assign inst_type_o = inst_type_i;
assign rd_w_ena_o = (rst == 1'b1)? 0 : rd_w_ena_i;
assign rd_w_addr_o = (rst == 1'b1)? 0 : rd_w_addr_i;
assign rd_w_data_o = (rst == 1'b1)? 0 : rd_w_data_i;
assign inst_o = inst_i;
assign pc_o = pc_i;


endmodule
